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obsolete rev. a information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of analog devices. a pkd01 one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781/329-4700 world wide web site: http://www.analog.com fax: 781/326-8703 ? analog devices, inc., 2001 monolithic peak detector with reset-and-hold mode functional block diagram + pkd01 output buffer output logic gnd c h det ?n +in ?n +in rst ?n +in output v+ v + + + cmp a b c v d 1 gated "g m " amp gated "g m " amp rst 0 0 1 1 det 0 1 1 0 operational mode peak detect peak hold reset indeterminate switches shown for: rst = ?,? det = ? features monolithic design for reliability and low cost high slew rate: 0.5 v/ s low droop rate t a = 25 c: 0.1 mv/ms t a = 125 c: 10 mv/ms low zero-scale error: 4 mv digitally selected hold and reset modes reset to positive or negative voltage levels logic signals ttl and cmos compatible uncommitted comparator on-chip available in die form general description the pkd01 tracks an analog input signal until a maximum amplitude is reached. the maximum value is then retained as a peak voltage on a hold capacitor. being a monolithic circuit, the pkd01 offers significant performance and package density advantages over hybrid modules and discrete designs without sacrificing system versatility. the matching characteristics attained in a monolithic circuit provide inherent advantages when charge injection and droop rate error reduction are primary goals. innovative design techniques maximize the advantages of mono- lithic technology. transconductance (g m ) amplifiers were chosen over conventional voltage amplifier circuit building blocks. the g m amplifiers simplify internal frequency compensation, minimize acquisition time and maximize circuit accuracy. their outputs are easily switched by low glitch current steering circu its. the steered outputs are clamped to reduce cha rge injection errors upon entering the hold mode or exiting the reset mode. the inher- ently low zero-scale error is further reduced by active zener-zap trimming to optimize overall accuracy. the output buffer amplifier features an fet input stage to reduce droop rate error during lengthy peak hold periods. a bias current cancellation circuit minimizes droop error at high ambi- ent temperatures. through the det control pin, new peaks may eit her be de tected or ignored. detected peaks are presented as positive output levels. positive or negative peaks may be detected without additional active circuits, since amplifier a can operate as an inverting or noninverting gain stage. an uncomm itted comparator provides many application o ptions. status indication and logic shaping/shifting are typical examples.
obsolete rev. a C2C pkd01?pecifications electrical characteristics pkd01a/e pkd01f parameter symbol conditions min typ max min typ max unit g m amplifiers a, b zero-scale error v zs 24 37mv input offset voltage v os 23 36mv input bias current i b 80 150 80 250 na input offset current i os 20 40 20 75 na voltage gain a v r l = 10 k ? , v o = 10 v 18 25 10 25 v/mv open-loop bandwidth bw a v = 1 0.4 0.4 mhz common-mode rejection ratio cmrr C10 v v cm +10 v 8090 7490 db power supply rejection ratio psrr 9 v v s 18 v 8696 7696 db input voltage range 1 v cm 10 11 10 11 v slew rate sr 0.5 0.5 v/ s feedthrough error 1 ? v in = 20 v, det = 1, rst = 0 66 80 66 80 db acquisition time to 0.1% accuracy 1 t aq 20 v step, a vcl = +1 41 70 41 70 s acquisition time to t aq 20 v step, a vcl = +1 45 45 s 0.01% accuracy 1 comparator input offset voltage v os 0.5 1.5 1 3 mv input bias current i b 700 1000 700 1000 na input offset current i os 75 300 75 300 na voltage gain a v 2k ? pull-up resistor to 5 v 5 7.5 3.5 7.5 v/mv common-mode rejection ratio cmrr C10 v v cm +10 v 82 106 82 106 db power supply rejection ratio psrr 9 v v s 18 v 7690 7690 db input voltage range 1 v cm 11.5 12.5 11.5 12.5 v low output voltage v ol i sink 5 ma, logic gnd = 0 v C0.2 +0.15 +0.4 C0.2 +0.15 +0.4 v off output leakage current i l v out = 5 v 2580 2580 a output short-circuit current i sc v out = 5 v 7 12 45 7 12 45 ma response time 2 t s 5 mv overdrive, 2 k ? pull-up 150 150 ns resistor to 5 v digital inputs C rst, det 2 logic 1 input voltage v h 22v logic 0 input voltage v l 0.8 0.8 v logic 1 input current i inh v h = 3.5 v 0.02 1 0.02 1 a logic 0 input current i inl v l = 0.4 v 1.6 10 1.6 10 a miscellaneous droop rate 3 v dr t j = 25 c 0.01 0.07 0.01 0.1 mv/ms t a = 25 c 0.02 0.15 0.03 0.20 mv/ms output voltage swing: v op det = 1 amplifier c r l = 2.5 k ? 11.5 12.5 11 12 v short-circuit current: amplifier c i sc 7 15 40 7 15 40 ma switch aperture time t ap 75 75 ns switch switching time ts 50 50 ns slew rate: amplifier c sr r l = 2.5 k ? 2.5 2.5 v/ s power supply current i sy no load 57 69ma notes 1 guaranteed by design. 2 det = 1, rst = 0. 3 due to limited production test times, the droop current corresponds to junction temperature (t j ). the droop current vs. time (after power-on) curve clarified this point. since most devices (in use) are on for more than 1 second, adi specifies droop rate for ambient temperature (t a ) also. the warmed-up (t a ) droop current specification is correlated to the junction temperature (t j ) value. adi has a droop current cancellation circuit that minimizes droop current at high temperature. ambient (t a ) temperature specifications are not subject to production testing. specifications subject to change without notice. (@ v s = 15 v, c h = 1000 pf, t a = 25 c, unless otherwise noted.)
obsolete rev. a C3C pkd01 electrical characteristics pkd01a/e pkd01f parameter symbol conditions min typ max min typ max unit g m amplifiers a, b zero-scale error v zs 47 612 mv input offset voltage v os 36 510 mv average input offset drift 1 tcv os C9 C24 C9 C24 v/ c input bias current i b 160 250 160 500 na input offset current i os 30 100 30 150 na voltage gain a v r l = 10 k ? , v o = 10 v 7.5 9 5 9 v/mv common-mode rejection ratio cmrr C10 v v cm +10 v 74 82 72 80 db power supply rejection ratio psrr 9 v v s 18 v 80 90 70 90 db input voltage range 1 v cm 10 11 10 11 v slew rate sr 0.4 0.4 v/ s acquisition time to 0.1% a ccuracy 1 t aq 20 v step, a vcl = +1 60 60 s comparator input offset voltage v os 2 2.5 2 5 mv average input offset drift 1 tcv os C4 C6 C4 C6 v/ c input bias current i b 1000 2000 1100 2000 na input offset current i os 100 600 100 600 na voltage gain a v 2 k ? pull-up resistor to 5 v 4 6.5 2.5 6.5 v/mv common-mode rejection ratio cmrr C10 v v cm +10 v 80 100 80 92 db power supply rejection ratio psrr 9 v v s 18 v 72 82 72 86 db input voltage range 1 v cm 11 11 v low output voltage v ol i sink 5 ma, logic gnd = 0 v C0.2 +0.15 +0.4 C0.2 +0.15 +0.4 v off output leakage current i l v out = 5 v 25 100 100 180 a output short-circuit current i sc v out = 5 v 6 10 45 6 10 45 ma response time t s 5 mv overdrive, 2 k ? pull-up resistor to 5 v 200 200 ns digital inputs C rst, det 2 logic 1 input voltage v h 22 v logic 0 input voltage v l 0.8 0.8 v logic 1 input current i inh v h = 3.5 v 0.02 1 0.02 1 a logic 0 input current i inl v l = 0.4 v 2.5 15 2.5 15 a miscellaneous droop rate 3 v dr t j = max operating temp. 1.2 10 3 15 mv/ms t a = max operating temp. det = 1 2.4 20 6 20 mv/ms output voltage swing amplifier c v op r l = 2.5 k ? 11 12 10.5 12 v short-circuit current amplifier c i sc 6 12406 1240 ma switch aperture time t ap 75 75 ns slew rate: amplifier c sr r l = 2.5 k ? 22v/ s power supply current i sy no load 5.5 8 6.5 10 ma notes 1 guaranteed by design. 2 det = 1, rst = 0. 3 due to limited production test times, the droop current corresponds to junction temperature (t j ). the droop current vs. time (after power-on) curve clarifies this point. since most devices (in use) are on for more than 1 second, adi specifies droop rate for ambient temperature (t a ) also. the warmed-up (t a ) droop current specification is correlated to the junction temperature (t j ) value. adi has a droop current cancellation circuit that minimizes droop current at high temperature. ambient (t a ) temperature specifications are not subject to production testing. specifications subject to change without notice. (@ v s = 15 v, c h = 1000 pf, ?5 c t a +125 c for pkd01ay, ?5 c t a +85 c for pkd01ey, pkd01fy and 0 c t a +70 c for pkd01ep, pkd01fp, unless otherwise noted.)
obsolete rev. a pkd01 C4C caution esd (electrostatic discharge) sensitive device. electrostatic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge without detection. although the pkd01 features proprietary esd protection circuitry, permanent damage may occur on devices subjected to high-energy electrostatic discharges. therefore, proper esd precautions are recommended to avoid performance degradation or loss of functionality. warning! esd sensitive device absolute maximum ratings 1, 2 supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 v input voltage . . . . . . . . . . . . . . . . . . . equal to supply voltage logic and logic ground voltage . . . . . . . . . . . . . . . . . . . . . . equal to supply voltage output short-circuit duration . . . . . . . . . . . . . . . . indefinite amplifier a or b differential input voltage . . . . . . . . . . 24 v comparator differential input voltage . . . . . . . . . . . . . 24 v comparator output voltage . . . . . . . . . . . . . . . . . . . . . . equal to positive supply voltage hold capacitor short-circuit duration . . . . . . . . . . indefinite lead temperature (soldering, 60 sec) . . . . . . . . . . . . . 300 c storage temperature range pkd01ay, pkd01ey, pkd01fy . . . . . C65 c to +150 c pkd01ep, pkd01fp . . . . . . . . . . . . . . . C65 c to +125 c operating temperature range pkd01ay . . . . . . . . . . . . . . . . . . . . . . . . C55 c to +125 c pkd01ey, pkd01fy . . . . . . . . . . . . . . . . C25 c to +85 c pkd01ep, pkd01fp . . . . . . . . . . . . . . . . . . . 0 c to 70 c junction temperature . . . . . . . . . . . . . . . . . C65 c to +150 c notes 1 absolute maximum ratings apply to both dice and packaged parts, unless otherwise noted. 2 stresses above those listed under absolute maximum ratings may cause perma- nent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. thermal characteristics package type ja * jc unit 14-lead hermetic dip (y) 99 12 c/w 14-lead plastic dip (p) 76 33 c/w * ja is specified for worst-case mounting conditions, i.e., ja is specified for device in socket for cerdip and pdip packages. ordering guide 1 temperature package package model 2 range description option pkd01ay C55 c to +85 c cerdip q-14 pkd01ey C25 c to +85 c cerdip q-14 pkd01fy C25 c to +85 c cerdip q-14 pkd01ep 0 c to 70 c plastic dip n-14 pkd01fp 0 c to 70 c plastic dip n-14 notes 1 burn-in is available on commercial and industrial temperature range parts in cerdip, plastic dip, and to-can packages. 2 for devices processed in total compliance to mil-std-883, add /883 after part number. consult factory for 883 data sheet. pin configuration det logic gnd comp out in c +in c in b +in b rst v+ output c h in a +in a v pkd01 dice characteristics
obsolete rev. a pkd01 C5C wafer test limits pkd01n parameter symbol conditions limit unit g m amplifiers a, b zero-scale error v zs 7mv max input offset voltage v os 6mv max input bias current i b 250 na max input offset current i os 75 na max voltage gain a v r l = 10 k ? , v o = 10 v 10 v/mv min common-mode rejection ratio cmrr C10 v v cm +10 v 74 db min power supply rejection ratio psrr 9 v v s 18 v 76 db min input voltage range 1 v cm 11.5 v min feedthrough error ? v in = 20 v, det = 1, rst = 0 66 db min comparator input offset voltage v os 3mv max input bias current i b 1000 na max input offset current i os 300 na max voltage gain 1 a v 2 k ? pull-up resistor to 5 v 3.5 v/mv min common-mode rejection ratio cmrr C10 v v cm +10 v 82 db min power supply rejection ratio psrr 9 v v s 18 v 76 db min input voltage range 1 v cm 11.5 v min low output voltage v ol i sink 5 ma, logic gnd = 5 v 0.4 v max C0.2 v min off output leakage current i l v out = 5 v 80 a max output short-circuit current i sc v out = 5 v 45 ma min 7 ma min digital inputsCrst, det 2 logic 1 input voltage v h 2v min logic 0 input voltage v l 0.8 v max logic 1 input current i inh v h = 3.5 v 1 a max logic 0 input current i inl v l = 0.4 v 10 a max miscellaneous droop rate 3 v dr t j = 25 c, 0.1 mv/ms max t a = 25 c 0.20 mv/ms max output voltage swing amplifier c v op r l = 2.5 k ? 11 v min short-circuit current amplifier c i sc 40 ma max 7 ma min power supply current i sy no load 9 ma max g m amplifiers a, b slew rate sr 0.5 v/ s acquisition time 1 t a 0.1% accuracy, 20 v step, a vcl = 1 41 s t a 0.01% accuracy, 20 v step, a vcl = 1 45 s comparator response time 5 mv overdrive, 2 k ? pull-up resistor to 5 v 150 ns miscellaneous switch aperture time t ap 75 ns switching time t s 50 ns buffer slew rate sr r l = 2.5 k ? 2.5 v/ s notes 1 guaranteed by design. 2 det = 1, rst = 0. 3 due to limited production test times, the droop current corresponds to junction temperature (t j ). the droop current vs. time (after power-on) curve clarifies this point. since most devices (in use) are on for more than 1 second, adi specifies droop rate for ambient temperature (t a ) also. the warmed-up (t a ) droop current specification is correlated to the junction temperature (t j ) value. adi has a droop current cancellation circuit that minimizes droop current at high temperature. ambient (t a ) temperature specifications are not subject to production testing. (@ v s = 15 v, c h = 1000 pf, t a = 25 c, unless otherwise noted.)
obsolete rev. a pkd01 C6C typical performance characteristics 18 14 18 46 18 91215 2 6 10 14 10 2 6 input + range = v+ 55 c t a +125 c v supply 55 c +25 c +125 c input range of amplifier v supply voltage +v and v v tpc 1. a and b input range vs. supply voltage frequency hz input noise voltage nv/ hz 1000 100 0 110 1k 100 10 r s = 10k r s = 0 tpc 4. input spot noise vs. frequency 1.0 1.0 +125 c +25 c 55 c 0.5 0.5 v in v error mv 0 10 50 510 polarity of error may be positive or negative c h = 1000pf t a = 25 c tpc 7. amplifier a charge injec- tion error vs. input voltage and temperature temperature c 6 6 75 50 125 25 0 25 50 75 100 4 2 0 2 4 offset voltage mv tpc 2. a and b amplifiers offset voltage vs. temperature bandwidth khz rms noise v 100 10 0 0.1 1 100 10 1 1000 v s = 15v t a = 25 c a v = +1 tpc 5. wideband noise vs. bandwidth supply voltage +v and v v output swing v 18 14 18 46 18 91215 2 6 10 14 10 2 6 v supply 55 c +25 c +125 c v+ supply 55 c +25 c +125 c r l = 10k tpc 8. output voltage swing vs. supply voltage (dual supply operation) temperature c a,b i os na 40 0 75 50 150 25 0 25 75 100 125 50 35 20 15 10 5 30 25 tpc 3. a, b i os vs. temperature 1.0 1.0 +125 c +25 c 55 c 0.5 0.5 v in v error mv 0 10 50 510 tpc 6. am plifier b charge injec- tion error vs. input voltage and temperature load resistor to ground k output swing volts 15 12.5 15 1.0 10.0 0.1 2.5 0 2.5 5.0 10.0 5.0 7.5 12.5 10.0 7.5 +25 c 55 c +125 c 55 c +25 c +125 c tpc 9. output voltage vs. load resistance
obsolete rev. a pkd01 C7C frequency hz pk of sinewave v 12 10 0 100 1k 1m 10k 100k 8 6 4 2 2mv error 200mv error 20mv error tpc 10. output error vs. frequency and input voltage 10 0% 100 90 t a = 25 c 0v time 20 s/div output voltage 5v/div tpc 13. large-signal inverting response t a = 25 c 0v time 20 s/div output voltage 5mv/div 10 0% 100 90 t a = 25 c tpc 16. settling time for +10 v to 0 v step input 10 0% 100 90 2 s 10mv c h = 1000pf peak output tpc 11. settling response 10 0% 100 90 t a = 25 c 0v time 20 s/div output voltage 5v/div tpc 14. large-signal noninverting response frequency hz gain db 90 60 30 1 10 10m 100 1k 10k 100k 1m 30 0 phase lag degrees 90 0 45 180 135 t a = 25 c r l = 10k c l = 30pf c h = 1000pf gain phase c h = 1000pf c h = 1000pf tpc 17. small-signal open-loop gain/phase vs. frequency 10 0% 100 90 2 s c h = 1000pf 10mv detected peak 3khz sinewave input 10mv 10v tpc 12. settling response 10 0% 100 90 time 20 s/div output voltage 5mv/div t a = 25 c 0v ()*+& - (
!+: :- frequency hz channel-to-channel isolation db 120 0 1 10 10m 100 1k 10k 100k 1m 100 80 60 40 20 t a = 25 c amplifier a(b) off, input = 20v p-p amplifier b(b) on, input = 0v test condition: c h = 1000pf amplifier a and b connected in +1 gain tpc 18. channel-to-channel isolation vs. frequency
obsolete rev. a pkd01 C8C tpc 26. comparator output response time (2 k ? pull-up resistor, t a = 25 c) tpc 27. comparator output response time (2 k ? pull-up resistor, t a = 25 c) tpc 24. acquisition of step input 10 0% 100 90 50 s 5v 10v 10v peak detect peak output reset input reset +10v 0v 10v +10v 0v 10v tpc 21. acquisition time vs. external hold capacitor and acquisition step tpc 23. droop rate vs. temperature tpc 20. droop rate vs. time after power on tpc 25. acquisition of sine wave peak 10 0% 100 90 50 s 5v detected peak reset +10v 0v 10v 5v c h = 1000pf 3khz sinewave input tpc 22. acquisition time vs. input voltage step size tpc 19. off isolation vs. frequency frequency hz off isolation db 100 80 0 1 10 10m 100 1k 10k 100k 1m 60 40 20 a, a v = +1 b, a v = 1 a, a v = 1 1v 5mv 50ns comparator output 5 +5 0 5 time 50ns/div 4 3 2 1 0 output voltage v input voltage mv 10 0% 100 90 50ns 1v 5mv comparator output 1v 5mv 50ns comparator output 5 +5 0 5 time 50ns/div 4 3 2 1 0 output voltage v input voltage mv 10 0% 100 90 50ns 1v 5mv comparator output temperature c droop rate (mv/sec), c h = 1000pf 10000 1000 1 100 50 50 0 100 100 500 ambient temperature junction temperature 10 input step v settling time s 50 20 40 30 5101520 0 10 0 t a = 25 c c h = 1000pf to 2mv to 20mv to 200mv hold capacitance pf acquisition time to 0.1% accuracy s 500 200 400 300 2000 4000 6000 8000 10000 0 100 80 60 40 20 0 20v step to 20mv (0.1%) 10v step to 10mv (0.1%) 5v step to 5mv (0.1%) 1v step to 1mv (0.1%) time after power applied minutes droop rate mv/ms 3 0 1 2 1 t a = 125 c c h = 1000pf 2345678910 0
obsolete rev. a pkd01 C9C supply voltage +v and v v input logic range v 18 10 18 46 9121518 2 10 14 6 2 6 14 +v in v+ for 55 c t a +125 c 55 c +125 c +25 c v tpc 28. input logic range vs. supply voltage supply +v and v v supply current ma 6 5 3121518 0 4 9 6 55 c +25 c +125 c tpc 31. supply current vs. supply voltage temperature c offset voltage mv 3 3 75 50 125 25 0 25 50 75 100 2 1 0 1 2 tpc 34. comparator offset voltage vs. temperature supply voltage +v and v v input range of logic ground v 18 14 46 9 12 18 15 14 2 0 2 6 10 6 10 18 v 55 c +125 c acceptable ground pin potential is between slide lines. +25 c +25 c +125 c v+ tpc 29. input range of logic ground vs. supply voltage frequency hz rejection ratio db 100 80 0 10 100 1m 1k 10k 100k 60 40 20 t a = 25 c v in = 0v c h = 1000pf channel a = 1 channel b = 0 positive supply (+15v +1v sin t) negative supply ( 15v +1v sin ) tpc 32. hold mode power supply rejection vs. frequency temperature c 110 50 75 50 150 25 0 25 75 100 125 50 100 80 70 60 90 comparator i os na tpc 35. comparator i os vs. temperature logic input voltage v logic current a 1 0 3 2 15 01234 1 2 logic ground = 0v logic 0 logic 1 55 c +125 c +25 c tpc 30. logic input current vs. logic input voltage input voltage v input bias current (either input) a 3 2 1 15 10 15 50 510 1 0 v s = 15v t a = 25 c other input at +10v other input at 10v other input at 0v input current must be limited to less than 1ma tpc 33. comparator input bias current vs. differential input voltage temperature c comparator i b na 1200 200 75 50 150 25 0 25 75 100 125 50 1000 800 600 400 tpc 36. comparator i b vs. temperature
obsolete rev. a pkd01 C10C supply voltage +v and v v output range of comparator v 18 10 18 46 9121518 2 10 14 6 2 6 14 v 55 c +25 c +125 c v+ +25 c +125 c tpc 37. output swing of com- parator vs. supply voltage i o output sink current ma 0.8 014 4 2 6 10 12 8 0.6 0.2 0 0.2 0.4 1.0 v o voltage output v dc 55 c +125 c +25 c tpc 40. comparator output voltage vs. output current and temperature time ns input voltage mv 5 50 300 50 0 100 200 250 150 4 2 1 0 3 +5 0 5 output voltage v pull-up resistor = 2k t a = +25 c t a = 55 c t a = +125 c tpc 38. comparator response time vs. temperature time ns input voltage mv 5 50 300 50 0 100 200 250 150 4 2 1 0 3 +5 0 5 output voltage v pull-up resistor = 2k t a = 55 c t a = +125 c t a = +25 c tpc 41. comparator response time vs. temperature input voltage mv 5 1.5 2.0 0.5 1.0 0 1.0 1.5 0.5 4 2 1 0 3 6 output voltage v v s = 15v t a = 25 c inverting input = v in noninverting input = 0v r l = 2k to 5v r l = 1k to 5v tpc 39. comparator transfer characteristic
obsolete rev. a pkd01 C11C theory of operation the typical peak detector uses voltage amplifiers and a diode or an emitter follower to charge the hold capacitor, c h , indirect- ionally (see figure 1). the output impedance of a plus d 1 s dynamic impedance, r d , make up the resistance which deter- mines the feedback loop pole. the dynamic impedance is r kt qi d d = , where i d is the capacitor charging current. the pole moves toward the origin of the s plane as i d goes to zero. the pole movement in itself will not significantly lengthen the acquisition time since the pole is enclosed in the system feedback loop. c h v out input v in v h v out (a) = v in (a) a v (a) a + c d 1 r out r d output figure 1. conventional voltage amplifier peak detector when the moving pole is considered with the typical frequency compensation of voltage amplifiers however, there is a loop stability problem. the necessary compensation can increase the required acquisition time. adis approach replaces the input voltage ampli- fier with a transconductance amplifier (see figure 2). the pkd01 transfer function can be reduced to: v v sc ggr sc g out in h mm out h m = ++ + 1 1 1 1 1 where: g m 1 a/mv, r out 20 m ? . the diode in series with as output (see figure 2) has no effect because it is a resistance in series with a current source. in addition to simplifying the system compensation, the input transconductance amplifier output current is switched by cur- rent steering. the steered output is clamped to reduce and match any charge injection. c h c r out i out d 1 input v in v h i out (a) = v in (a) g m (a) a v out output figure 2. transconductance amplifier peak detector figure 3 shows a simplified schematic of the reset g m amplifier, b. in the track mode, q 1 and q 4 are on and q 2 and q 3 are off. a current of 2i passes through d 1 , i is summed at b and passes through q 1 , and is summed with g m v in . the current sink can absorb only 3i, thus the current passing through d 2 can only be: 2k C g m v in . the net current into the hold capacitor node then, is g m v in [i h = 2i C (2i C g m v in )]. in the hold mode, q 2 and q 3 are on while q 1 and q 4 are off. the net current into the top of d 1 is Ci until d 3 turns on. with q 1 off, the bottom of d 2 is pulled up with a current i until d 4 turns on, thus, d 1 and d 2 are reverse biased by <0.6 v, and charge injec- tion is independent of input level. the monolithic layout results in points a and b having equal nodal capacitance. in addition, matched diodes d 1 and d 2 have equal diffusion capacitance. when the transconductance ampli- fier outputs are switched open, points a and b are ramped equally, but in opposite phase. diode clamps d 3 and d 4 cause the swings to have equal amplitudes. the net charge injection (voltage change) at node c is therefore zero. v+ g m v in v in 3i 3i v i 2i d 3 d 1 d 4 c h c q 1 q 2 q 3 q 4 a b logic control a > b = peak detect a < b = peak hold a d 2 c b 6 figure 3. transconductance amplifier with low glitch current switch the peak transconductance amplifier, a is shown in figure 4. unidirectional hold capacitor charging requires diode d 1 to be connected in series with the output. upon entering the peak hold mode d 1 is reverse-biased. the voltage clamp limits charge injection to approximately 1 pc and the hold step to 0.6 mv. minimizing acquisition time dictates a small c h capacitance. a 1000 pf value was selected. droop rate was also minimized by providing the output buffer with an fet input stage. a cur- rent cancellation circuit further reduces droop current and minimizes the gate currents tendency to double for every 10 temperature change. g m v in v in 3i 3i v v+ i 2i d 3 d 1 d 2 d 4 c h c q 1 q 2 q 3 q 4 a b logic control a > b = peak detect a < b = peak hold r d 6 figure 4. peak detecting transconductance amplifier with switched output
obsolete rev. a pkd01 C12C applications information optional offset voltage adjustment offset voltage is the primary zero scale error component since a variable voltage clamp limits voltage excursions at d 1 s anode and reduces charge injection. the pkd01 circuit gain and opera- tional mode (positive or negative peak detection) determine the applicable null circuit. figures 5 through 8 are suggested circuits. each circuit also corrects amplifier c offset voltage error. a. nulling gated output g m amplifier a . diode d 1 must be conducting to close the feedback circuit during amplifier a v os adjustment. resistor network r a C r c cause d 1 to conduct slightly. with det = 0 and v in = 0 v, monitor the pkd01 output. adjust the null potentiometer until v out = 0 v. after adjustment, disconnect r c from c h . b. nulling gated g m amplifier b. set amplifier b signal input to v in = 0 v and monitor the pkd01 output. set det = 1, rst = 1 and adjust the null potentiometer for v out = 0 v. the circuit gaininverting or noninvertingwill determine which null circuit illustrated in figures 5 through 8 is applicable. pkd01 d 1 c h 1000pf c a b v out v s v s + 0.1 f det r1 1k rst 15v r c 2m r a 200k r b 1k notes: 1. null range = v s ( ) 2. disconnect r c from c h after amplifier a adjustment. 3. repeat null circuit for reset buffer amplifier b if required. r a , r b and r c not necessary for amplifier b adjustment. v in + r1 1k r2 2m 100k r1 r2 figure 5. v os null circuit for unity gain positive peak detector pkd01 d 1 c h 1000pf c a b v out r2 = r3 + r4 v s v s + 25k r4 20 0.1 f det r1 rst 15v r c 2m r a 200k r b 1k notes: 1. null range = v s ( )( ) 2. disconnect r c from c h after amplifier a adjustment. 3. repeat null circuit for reset buffer amplifier b if required. r1 v in v in + r5 20k r3 r5 r4 r1 r1 + r3 figure 6. v os null circuit for differential peak detector pkd01 d 1 c h 1000pf c a b v out r2 v in r1 0.1 f v s v s + 25k det r3 20k rst 15v r c 2m r a 200k r b 1k notes: 1. null range = v s ( ) 2. disconnect r c from c h after amplifier a adjustment. 3. repeat null circuit for reset buffer amplifier b if required. r4 r3 r4 20 figure 7. v os null circuit for negative peak detector pkd01 d 1 c h 1000pf c a b v out r2 v in r1 r5 20k r3 20 0.1 f v s v s + 25k det r4 = r2 r1 r1 + r2 r4 rst 15v r c 2m r a 200k r b 1k gain = 1 + r2 r1 + r3 notes: 1. null range = v s ( ) 2. disconnect r c from c h after amplifier a adjustment. 3. repeat null circuit for reset buffer amplifier b if required. r3 r5 figure 8. v os null circuit for positive peak detector with gain
obsolete rev. a pkd01 C13C peak hold capacitor recommendations the hold capacitor (c h ) serves as the peak memory element and compensating capacitor. stable operation requires a mini- mum value of 1000 pf. larger capacitors may be used to lower droop rate errors, but acquisition time will increase. zero scale error is internally trimmed for c h = 1000 pf. other c h values will cause a zero scale shift which can be approxi- mated with the following equation. ? vmv pc cnf mv zs h () = () () ? 110 06 3 . the peak hold capacitor should have very high insulation resis- tance and low dielectric absorption. for tem peratures below 85 c, a polystyrene capacitor is recommended, while a teflon capacitor is recommended for high temperature environments. capacitor guarding and ground layout ground planes are recommended to minimize ground path resistance. separate analog and digital grounds should be used. the two ground systems are tied together only at the common system ground. this avoids digital currents returning to the system ground through the analog ground path. pkd01 c h repeat on component side of pc board if possible bottom view 14 13 12 11 10 9 8 1 2 3 4 5 6 7 figure 9. c h terminal (pin 4) guarding. see text. the c h terminal (pin 4) is a high impedance point. to minimize gain errors and maintain the pkd01s inherently low droop rate, guarding pin 4 as shown in figure 9 is recommended. comparator the comparator output high level (v oh ) is set by external resis- tors. it is possible to optimize noise immunity while interfacing to all standard logic familiesttl, dtl, and cmos. figure 10 shows the comparator output with external level-setting resistors. table i gives typical r1 and r2 values for common circuit conditions. the maximum comparator high output voltage (v oh ) should be limited to: v oh ( maximum ) < v + C2.0 v with the comparator in the low state (v ol ), the output stage will be required to sink a current approximately equal to v c /r1. cmp pkd01 comparator input inverting comparator input digital gnd v r1 = r2 ( ) v c v oh 1 r1 r2 v oh v c figure 10. comparator output with external level-setting resistors table i. v c v oh r1 r2 5 3.5 2.7 k ? 6.2 k ? 5 5.0 2.7 k ? 15 3.5 4.7 k ? 1.5 k ? 15 5.0 4.7 k ? 2.4 k ? 15 7.5 7.5 k ? 7.5 k ? 15 10.0 7.5 k ? 15 k ? peak detector logic control (rst, det ) the transconductance amplifier outputs are controlled by the digital logic signals rst and det . the pkd01 operational mode is selected by steering the current (i 1 ) through q 1 and q 2 , thus providing high-speed switching and a predictable logic threshold. the logic threshold voltage is 1.4 v when digital ground is at zero volts. other threshold voltages (v th ) may be selected by applying the formula: v th 1.4 v + digital ground potential . for proper operation, digital ground must always be at least 3.5 v below the positive supply and 2.5 v above the negative supply. the rst or det signal must always be at least 2.8 v above the negative supply. operating the digital ground at other than zero volts does influence the comparator output low voltage. the v ol level is re ferenced to digital ground and will follow any changes in d igital ground potential: v ol 0.2 v + digital ground potential . r v i c sink 1 r v v c oh 2 1 1 ? ? ? ? ? ? ? ? ? ? ?
obsolete rev. a pkd01 C14C typical circuit configurations v+ det or rst current to control modes q 2 q 1 i 1 i 2 d q 3 v digital ground figure 11. logic control input det /rst pkd01 d 1 c h 1000pf c a b reset vo ltag e v+ v output a gain = +1 b gain = +1 0v +10v 0v +10v input output time 50 s/div figure 13. unity gain positive peak detector 10k 1% input (gain = +2) det pkd01 d 1 c h 1000pf c a b 10k 5% 40.2k 1% 5.1k 5% 10k 1% reset voltage = +1v (resets to 4v) 8.2k 5% rst v+ v output a gain = +2 b gain = 4 +5v 0v 2v +10v 0v 4v 10v input output time 50 s/div figure 14. positive peak detector with gain 2 3 4 5 6 7 14 13 12 11 10 9 8 1 pkd01 56k 5% 36k 5% 18k 5% +18v 18v figure 12. burn-in circuit
obsolete rev. a pkd01 C15C 20k 1% input (gain = 2) det /rst pkd01 d 1 c h 1000pf c a b 8.2k 5% 30.1k 1% 10k 1% 10k 1% reset voltage = 1v (resets to 4v) 7.5k 5% rst v+ v output a gain = 2 b gain = +4 +2v 0v 5v +10v 0v 4v 10v input output time 50 s/div figure 15. negative peak detector with gain 10k 1% v in det pkd01 d 1 c h 1000pf c a b 10k 5% 10k 1% reset vo ltag e v+ v output a gain = 1 b gain = +1 0v +10v 0v 10v input output time 50 s/div figure 16. unity gain negative peak detector pkd01 c h 1000pf c a b reset vo ltag e output input amplifier gain reset amplifier gain = 1 + r3 = r4 = 1 + r2 r4 input r1 1 r1 1 r2 r2 r1 r3 if both input signal (amplifier a input) and the reset voltage (amplifier b input) have the same positive voltage gain, the gain can be set by a single voltage divider for both input amplifiers. note: r1, r2, r3 and r4 > 5k figure 17. alternate gain configuration
obsolete rev. a pkd01 C16C op27 pkd01 positive peak detector pkd01 negative peak detector v in v pk + v pk 10k 10k 10k 10k v out v pk + v pk + v in v pk + v pk figure 18. peak-to-peak detector notes: 1. device is reset to 0 volts. 2. detected peaks are presented as positive output levels. 3. r = 10k . 1000pf polystyrene c h output peak detector reset +15v 15v 10.5k +15v pos/ neg peak detector sw-02 s2 s1 s3 s4 r r input 15v pkd01 figure 19. logic selectable positive or negative peak detector 5v 2.7k input signal reset vo ltag e rst det bit 1 bit 10 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 port 1 port 0 processor pkd01 d 1 c h r r dac10 c cmp a b figure 20. peak reading a/d converter
obsolete rev. a pkd01 C17C pkd01 a b c logic gnd analog gnd 15v +15v v out 5v 1ms 2v input reset output peak detect notes: reset voltage = 1.0v trace 1 = 2v/div trace 2 = 5v/div trace 3 = 2v/div sw-201 15v +15v v rs 1 v rs 2 v rs 3 v rs 4 v in a1 a2 a3 a4 pk det /rst figure 21. positive peak detector with selectable reset voltage pkd01 d 1 c h dac08 c a b det ramp start pulse buffered ramp output ramp slope selection i b1 b8 r > 20k ref-01 15v a0 a1 a2 ch1 ch2 ch3 ch4 ch5 ch6 ch7 ch8 mux-08 amplitude selection logic ramp amplitude slope = i 0 c ~0.5v/ s ~0.5v/ s slope = i 1 c ramp amplitude ramp start pulse 0 notes: 1. negative slope of ramp is set by dac08 output current. 2. dac08 is a digitally controlled current generator. the maximum full-scale current must be less than 0.5ma. rst figure 22. programmable low frequency ramp generator
obsolete rev. a pkd01 C18C outline dimensions dimensions shown in inches and (mm). 14-lead plastic dip (pdip) (n-14) 14 17 8 pin 1 0.795 (20.19) 0.725 (18.42) 0.280 (7.11) 0.240 (6.10) 0.100 (2.54) bsc seating plane 0.060 (1.52) 0.015 (0.38) 0.210 (5.33) max 0.022 (0.558) 0.014 (0.356) 0.160 (4.06) 0.115 (2.93) 0.070 (1.77) 0.045 (1.15) 0.130 (3.30) min 0.195 (4.95) 0.115 (2.93) 0.015 (0.381) 0.008 (0.204) 0.325 (8.25) 0.300 (7.62) 14-lead cerdip (q-14) 14 17 8 0.310 (7.87) 0.220 (5.59) pin 1 0.005 (0.13) min 0.098 (2.49) max 0.100 (2.54) bsc 15 0 0.320 (8.13) 0.290 (7.37) 0.015 (0.38) 0.008 (0.20) seating plane 0.200 (5.08) max 0.785 (19.94) max 0.150 (3.81) min 0.200 (5.08) 0.125 (3.18) 0.023 (0.58) 0.014 (0.36) 0.070 (1.78) 0.030 (0.76) 0.060 (1.52) 0.015 (0.38) c00481-0-2/01 (rev. a) printed in u.s.a.

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